A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. The multiple cycle memory access unit preferably aborts operation, stops and saves its internal state on a predetermined event.