发明授权
US06345005B2 Integrated circuit with efficient testing arrangement 失效
具有高效测试布置的集成电路

  • 专利标题: Integrated circuit with efficient testing arrangement
  • 专利标题(中): 具有高效测试布置的集成电路
  • 申请号: US09734925
    申请日: 2000-12-13
  • 公开(公告)号: US06345005B2
    公开(公告)日: 2002-02-05
  • 发明人: Aki UrakamiMichio Nakajima
  • 申请人: Aki UrakamiMichio Nakajima
  • 优先权: JP12-019170 20000127
  • 主分类号: G11C700
  • IPC分类号: G11C700
Integrated circuit with efficient testing arrangement
摘要:
A read and write control circuit receives (m×n))-bit data output m-bit parallel from a D flip flop, and a q-bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x+1) bits in a total of 2q operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x+1)>m and n>2q, where m, n, x and 1 indicate positive integers and (x+1)>m and n>2q. The data written to the memory circuits is read out in units of integral multiples of (x+1) bits in a total of 2q operations.
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