发明授权
- 专利标题: Integrated circuit with efficient testing arrangement
- 专利标题(中): 具有高效测试布置的集成电路
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申请号: US09734925申请日: 2000-12-13
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公开(公告)号: US06345005B2公开(公告)日: 2002-02-05
- 发明人: Aki Urakami , Michio Nakajima
- 申请人: Aki Urakami , Michio Nakajima
- 优先权: JP12-019170 20000127
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
A read and write control circuit receives (m×n))-bit data output m-bit parallel from a D flip flop, and a q-bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x+1) bits in a total of 2q operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x+1)>m and n>2q, where m, n, x and 1 indicate positive integers and (x+1)>m and n>2q. The data written to the memory circuits is read out in units of integral multiples of (x+1) bits in a total of 2q operations.
公开/授权文献
- US20010043485A1 Integrated circuit with efficient testing arrangement 公开/授权日:2001-11-22