An optimal buffer is chosen for insertion at a node by calculating a &pgr;-model of a downstream circuit to a child node where the &pgr;-model contains at least a capacitance value. The gate delay is computed at the node using an effective capacitance derived from the &pgr;-model and buffer characteristics of a particular buffer. The interconnect delay is then computed from sets of moments associated with each gate downstream from the node via a bottom-up incremental technique. Slack is computed using the gate delay for the child node and the interconnect delay for the child node and then the computed slack is compared to the slack of other buffers at the node. The node may be a sink or have one or two children.