发明授权
US06348374B1 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
失效
具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
- 专利标题: Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
- 专利标题(中): 具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
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申请号: US09597887申请日: 2000-06-19
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公开(公告)号: US06348374B1公开(公告)日: 2002-02-19
- 发明人: Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
- 申请人: Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
- 主分类号: H01L218242
- IPC分类号: H01L218242
摘要:
A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
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