发明授权
US06350684B1 Graded/stepped silicide process to improve MOS transistor 有权
分级/步进硅化处理以改善MOS晶体管

  • 专利标题: Graded/stepped silicide process to improve MOS transistor
  • 专利标题(中): 分级/步进硅化处理以改善MOS晶体管
  • 申请号: US09594868
    申请日: 2000-06-15
  • 公开(公告)号: US06350684B1
    公开(公告)日: 2002-02-26
  • 发明人: Fuchao WangMing Fang
  • 申请人: Fuchao WangMing Fang
  • 主分类号: H01L2144
  • IPC分类号: H01L2144
Graded/stepped silicide process to improve MOS transistor
摘要:
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner suicides with less likelihood of delamination or metal oxidation may thus be formed.
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