发明授权
US06352916B1 Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench 失效
通过从沟槽部分去除导电材料在多层互连结构中形成插塞的方法

  • 专利标题: Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench
  • 专利标题(中): 通过从沟槽部分去除导电材料在多层互连结构中形成插塞的方法
  • 申请号: US09432516
    申请日: 1999-11-02
  • 公开(公告)号: US06352916B1
    公开(公告)日: 2002-03-05
  • 发明人: Sanh D. TangRajendra Narasimhan
  • 申请人: Sanh D. TangRajendra Narasimhan
  • 主分类号: H01L214763
  • IPC分类号: H01L214763
Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench
摘要:
In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.
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