A method of fabricating a vertical transistor of a memory cell is disclosed. A pad layer is formed on the substrate. A deep trench is formed in the substrate. A trench capacitor is formed in the deep trench. A collar oxide layer is formed on the sidewalls at the upper portion of the trench capacitor. A first conductive layer and a first opening are formed on the trench capacitor. A second conductive layer is formed to fill the first opening. An ARC layer and a photoresist layer are coated and defined to form a second opening. The layers under the second opening are defined to form a third opening. A first insulating layer is formed to fill the third opening. The first insulating layer and the second conductive layer are partially removed to form the shallow trench isolation. The residual second conductive layer is etched back to form a buried strap and a fourth opening. After forming the insulating spacers on the sidewalls of the fourth opening, a second insulating layer is formed on the buried strap. The pad layer and the insulating spacer are removed. A third insulating layer is formed on the substrate. A well is form at the upper portion of the substrate, the third insulating layer is removed. A fourth insulating layer is formed and partially removed to form the gate oxide. Third and fourth conductive layers are formed to fill the fourth opening and defined to form the gate. Source/drain regions and gate spacers are formed.