发明授权
- 专利标题: Method of manufacturing a semiconductor component and plating tool therefor
- 专利标题(中): 制造半导体部件及其电镀工具的方法
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申请号: US09451552申请日: 1999-12-01
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公开(公告)号: US06361675B1公开(公告)日: 2002-03-26
- 发明人: Timothy Lee Johnson , Joseph English , David Austin , George F. Carney , Kandis Mae Knoblauch , Douglas G. Mitchell
- 申请人: Timothy Lee Johnson , Joseph English , David Austin , George F. Carney , Kandis Mae Knoblauch , Douglas G. Mitchell
- 主分类号: C25D502
- IPC分类号: C25D502
摘要:
A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.
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