A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes, to form pairs of heavily doped elongated source regions of the first conductivity type which extend along said two elongated edges of each elongated window and which are separated by said central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially symmetrically tilted of a second prescribed angle with respect to said orthogonal direction, to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions extending under the two elongated edges of each elongated window; implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the elongated windows.