A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.