A clock generator for a multi-system comprising a TCXO (temperature compensated crystal oscillator) 1 controlled by an AFC (automatic frequency control) circuit 12 and a sub-system operative with a system clock supplied from the main system and including a PLL (phase locked loop) circuit having a phase comparator 5 and a VCO (voltage controlled oscillator) 3 is disclosed. The frequency division ratios of frequency dividers 2, 4 in the PLL circuit is compensated on the basis of the output of the AFC circuit 12 to absorb phase changes due to the AFC circuit 12.