发明授权
- 专利标题: Patterning method in semiconductor device fabricating process
- 专利标题(中): 半导体器件制造工艺中的图案化方法
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申请号: US09317855申请日: 1999-05-25
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公开(公告)号: US06376155B2公开(公告)日: 2002-04-23
- 发明人: Katsuyuki Ito
- 申请人: Katsuyuki Ito
- 优先权: JP10-142970 19980525
- 主分类号: G03F726
- IPC分类号: G03F726
摘要:
In a semiconductor device fabricating process, a chemical amplification resist layer is formed on an insulating film formed on a semiconductor substrate, and the chemical amplification resist layer is patterned to form an opening. The insulating film formed on the semiconductor substrate is wet-etched using the patterned chemical amplification resist layer as a mask. Before the wet-etching is carried out, a surface treatment is conducted for the patterned chemical amplification resist layer to form an insoluble layer at a surface of the patterned chemical amplification resist layer, thereby to elevate a wet-etching-resistance of the patterned chemical amplification resist layer. Thus, deformation of a resist pattern formed of the patterned chemical amplification resist layer is prevented in the wet etching process, so that an opening pattern of a desired shape is formed in the insulating film.
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