Invention Grant
US06387797B1 Method for reducing the capacitance between interconnects by forming voids in dielectric material 失效
通过在介电材料中形成空隙来减小互连之间的电容的方法

  • Patent Title: Method for reducing the capacitance between interconnects by forming voids in dielectric material
  • Patent Title (中): 通过在介电材料中形成空隙来减小互连之间的电容的方法
  • Application No.: US09234292
    Application Date: 1999-01-20
  • Publication No.: US06387797B1
    Publication Date: 2002-05-14
  • Inventor: Subhas BothraRao Annapragada
  • Applicant: Subhas BothraRao Annapragada
  • Main IPC: H01L214763
  • IPC: H01L214763
Method for reducing the capacitance between interconnects by forming voids in dielectric material
Abstract:
A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.
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