Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal

发明授权

US06393080B1 Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal 有权

标题翻译：装置包括时钟控制电路和使用与外部时钟信号同步的内部时钟信号的装置

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专利标题： Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal
专利标题（中）： 装置包括时钟控制电路和使用与外部时钟信号同步的内部时钟信号的装置
申请号： US09271329

申请日： 1999-03-18
公开(公告)号： US06393080B1

公开(公告)日： 2002-05-21
发明人: Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
申请人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
优先权： JP10-069059 19980318
主分类号： H04L700
IPC分类号： H04L700

Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal

摘要：

A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

摘要（中）：

状态保持电路初始化电路在正向脉冲传播到最后一级的正向脉冲延迟电路时，初始化状态保持电路。通过该操作，从恢复从接收器输出的短时间内建立同步。状态保持电路控制电路还控制状态保持电路的复位定时。正向脉冲调整电路控制要提供给正向脉冲延迟线的正向脉冲的脉冲宽度。通过该动作，从产生向后脉冲的阶段到第一阶段的阶段被牢固地转到设定状态，从而能够建立向后脉冲的传播和同步。因此，即使从接收器的输出停止或外部时钟信号的占空比很重，也能够可靠地建立同步。

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