A method and system for managing metal resources in the physical design of integrated circuits is presented. Percent metal usage is allocated for intra-block routing use by each functional block. Power and clock grids are established. Block designers coordinate the locations of signal ports of the blocks so as to avoid blocking any inter-block signals, areas of metal are then reserved for ports and intra-block signals. The inter-block signals are then pre-routed, avoiding the power grid, clock grid, and reserved intra-block routing metal. If any problem nets emerge from the pre-routing, better port locations and sub-block placement within the respective blocks are determined and the process is repeated.