发明授权
- 专利标题: Test structures for electrical linewidth measurement and processes for their formation
- 专利标题(中): 电线宽测量的测试结构及其形成过程
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申请号: US09912186申请日: 2001-07-24
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公开(公告)号: US06399401B1公开(公告)日: 2002-06-04
- 发明人: Jongwook Kye , Harry Levinson
- 申请人: Jongwook Kye , Harry Levinson
- 主分类号: G01R3126
- IPC分类号: G01R3126
摘要:
In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.