发明授权
- 专利标题: Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions
- 专利标题(中): 添加平面化电介质层以减少在形成浅沟槽隔离区域期间的化学机械程序期间经历的凹陷现象
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申请号: US09759905申请日: 2001-01-16
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公开(公告)号: US06399461B1公开(公告)日: 2002-06-04
- 发明人: Pao-Kuo Liu , Ja-Rong Hsieh , Zhi-Yong Wang
- 申请人: Pao-Kuo Liu , Ja-Rong Hsieh , Zhi-Yong Wang
- 主分类号: H01L2176
- IPC分类号: H01L2176
摘要:
A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.
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