发明授权
- 专利标题: Transmission device and integrated circuit
- 专利标题(中): 传输设备和集成电路
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申请号: US09903004申请日: 2001-07-11
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公开(公告)号: US06400614B1公开(公告)日: 2002-06-04
- 发明人: Masaki Hiromori , Seiji Matsuzaki , Toshiaki Asai , Yoshinari Oshio , Masato Hashizume , Megumi Shibata , Yuji Kamura
- 申请人: Masaki Hiromori , Seiji Matsuzaki , Toshiaki Asai , Yoshinari Oshio , Masato Hashizume , Megumi Shibata , Yuji Kamura
- 优先权: JP2001-076761 20010316
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.