A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the resistive ferroelectric memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first electrode and a second electrode. The first electrode is supplied with a fixed cell plate voltage. The second electrode is connected to the given zone of the first conductivity type. A semiconductor body of a second conductivity type opposite the first conductivity type is provided. A line is formed by a highly doped zone of the first conductivity type. The line is supplied with the cell plate voltage. The second electrode of the storage capacitor is connected via the resistor to the line.