发明授权
- 专利标题: Method and apparatus for compacting wiring layout
- 专利标题(中): 用于压实布线布局的方法和装置
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申请号: US09047491申请日: 1998-03-25
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公开(公告)号: US06412095B1公开(公告)日: 2002-06-25
- 发明人: Hiroyuki Tada
- 申请人: Hiroyuki Tada
- 优先权: JP9-259065 19970924
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
Compacting a wiring layout of semiconductor integrated circuit having at least two metal layers in which two first layer wires of the same wiring are originally arranged at different locations and connected together by a second layer wire. First layer wires of other wiring are identified that interfere with a line extending from one of the two first layer wires and forms an enlarged area between the obstructed first layer wired and the interfering first layer wire. Next, the other one of the two first layer wires is shifted to the enlarged area to be aligned along the same line with the obstructed first layer wire. Then, the second layer wire which previously connected the two first layer wires is deleted.
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