发明授权
- 专利标题: Low cost and high speed 3-load printed wiring board bus topology
- 专利标题(中): 低成本和高速3负载印刷线路板总线拓扑
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申请号: US09596613申请日: 2000-06-19
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公开(公告)号: US06417462B1公开(公告)日: 2002-07-09
- 发明人: Sanjay Dabral , Ming Zeng
- 申请人: Sanjay Dabral , Ming Zeng
- 主分类号: H01R909
- IPC分类号: H01R909
摘要:
A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.