A method of inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. In this method, a conductive target attribute is formed on a first alignment portion of the wafer-in-process. A contact attribute is formed on the upper process layer through which an electric path can be established with the target attribute in an acceptable alignment situation but cannot established in an unacceptable alignment situation. By attempting to establish an electric path from the target attribute through the contact attribute, the accuracy of alignment can be determined based on whether or not an electrical path is established. The target attribute may be a series of conductive strips and the contact attribute may be a series of contact holes that will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation. The overlay arrangement may be such that the magnitude and/or direction of misalignment may be determined by the electrical path arrangement that is established during the inspection process.