发明授权
- 专利标题: Process for fabricating capacitor
- 专利标题(中): 制造电容器的工艺
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申请号: US09538911申请日: 2000-03-30
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公开(公告)号: US06432794B1公开(公告)日: 2002-08-13
- 发明人: Chine-Gie Lou
- 申请人: Chine-Gie Lou
- 优先权: TW88120697A 19991126
- 主分类号: H01L2120
- IPC分类号: H01L2120
摘要:
A process for fabricating a capacitor suitable for forming a bottom electrode layer of the capacitor on a substrate. First, a first dielectric layer is formed on a substrate. Then, a portion of the first dielectric layer is removed to form a contact hole. A conductive plug is formed within the contact hole. A seed layer is formed on the conductive plug. A sacrifice layer is formed on both the seed layer and the first dielectric layer. A predetermined region of the sacrifice layer is removed to form a recess so as to expose the seed layer. Then, a bottom electrode layer is formed by electroplating within the recess. The sacrifice layer is removed afterwards. Finally, a second dielectric layer and a top electrode layer are formed on the bottom electrode layer in sequence. The present invention is characterized in that it does not require a direct etching process on a platinum material to. form the bottom electrode layer. As a result, problems encountered during the platinum etching process such as the difficulty in controlling the critical dimension of an etched platinum bottom electrode layer can be overcome.
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