An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation step to repair discontinuities in a copper seed layer, superfill plating to fill the smallest features, reverse plating to remove the adsorbed plating additives and their by-products from the substrate, a second superfill plating to fill intermediate size features, a second reverse plating to remove adsorbed plating additives and their by-products from the substrate, and a bulk fill plating with high current density to fill large features. The superfill and reverse plating operations may be repeated more than twice prior to bulk filling in order to provide the desired surface morphology.