- 专利标题： Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers
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申请号： US09769814申请日： 2001-01-26
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公开(公告)号： US06440800B1公开(公告)日： 2002-08-27
- 发明人: James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
- 申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
- 主分类号： H01L21336
- IPC分类号： H01L21336
摘要：
A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.
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