发明授权
US06441667B1 Multiphase clock generator 失效
多相时钟发生器

Multiphase clock generator
摘要:
The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
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