A digital demodulator (100) includes a differentiate and cross multiply stage (102) and a plurality of filter/decimator stages (106, 112, 118 and 108, 114, 120 and 110, 116, 122) that accept both multiple baud rates and multiple modulation deviation frequencies, and that provide a common frequency data stream at their respective outputs. One of said filter/decimator stages is coupled to a primary filter (124) which is followed by a box filter (134). The box filter (134) improves the overall filter response and provides notches at a specified frequency (e.g., 4800 Hz) and its harmonics. Demodulator (100) provides improved sensitivity without the need for any circuit trimming. The filter stages (e.g., 106, 112, 118; 108, 114, 120; and 110, 116, 122) used in demodulator (100) have been optimized to eliminate the need for costly multipliers.