发明授权
US06442645B1 Pre-decode conditional command generation for reduced SDRAM cycle latency
失效
预解码条件命令生成以减少SDRAM周期延迟
- 专利标题: Pre-decode conditional command generation for reduced SDRAM cycle latency
- 专利标题(中): 预解码条件命令生成以减少SDRAM周期延迟
-
申请号: US09205447申请日: 1998-12-04
-
公开(公告)号: US06442645B1公开(公告)日: 2002-08-27
- 发明人: David E. Freker
- 申请人: David E. Freker
- 主分类号: G06F1200
- IPC分类号: G06F1200
摘要:
A method and apparatus for reducing the latency of a cycle initiated by a bus-mastering agent to a memory array is described. The method and corresponding apparatus involves partially decoding a current memory cycle to generate intermediate signals and providing one or more “safe” indicator signals indicating the status of a previous memory cycle. A circuit receives the intermediate signals and the one or more safe indicator signals, and determines whether it is safe to issue a chip select to the memory array, notwithstanding the fact that the command to be issued to the memory array is not yet known. If the cycle is a page-hit, then no further commands or chip select signals are required for the balance of the memory cycle. If the cycle is a row-miss or page-miss, further chip select assertions are required and the responsibility to assert the chip select signal is transferred from the device to a finite state machine.