发明授权
US06444571B1 Process for fabricating a semiconductor device with improved step coverage and reliability of a lower aluminum line
失效
制造半导体器件的工艺，其具有改进的下层铝线的台阶覆盖率和可靠性
- 专利标题： Process for fabricating a semiconductor device with improved step coverage and reliability of a lower aluminum line
- 专利标题（中）： 制造半导体器件的工艺，其具有改进的下层铝线的台阶覆盖率和可靠性
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申请号： US09449236申请日： 1999-11-24
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公开(公告)号： US06444571B1公开(公告)日： 2002-09-03
- 发明人: Yoshiaki Yamamoto
- 申请人： Yoshiaki Yamamoto
- 优先权： JP10-337804 19981127
- 主分类号： H01L214763
- IPC分类号： H01L214763
摘要：
A lower aluminum line is exposed to a via-hole formed in an inter-level insulating layer, and an outgassing is carried out before deposition for an upper aluminum line connected through the via-hole to the lower aluminum line, wherein the outgassing is carried out at a substrate temperature equal to or less than the maximum substrate temperature in the formation of the inter-level insulating layer so that a hillock and a whisker due to the thermal stress do not take place in the lower aluminum line.
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