A memory device includes a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element from the data array based on the read command. The delay locked loop circuit is adapted to receive the external clock signal and delay the external clock signal by a programmable amount to generate a delay locked loop clock signal. The timing control logic is adapted to generate a first input enable signal based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first storage device adapted to receive the first data element. The first storage device has an input terminal enabled in response to the first input enable signal and an output terminal enabled in response to the first output enable signal.