A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.