A data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any interruption and to transfer continuous data on a general-purpose bus such as a PCI bus, and a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or the data transfer system. If it is supposed that a capacity of a write buffer memory 4 is CAPW, an input rate of continuously input data is T1, and a maximum assumed value of an interval of bus access permissions issued by a CPU 1 is TW, data omissions can be prevented by setting CAPW, T1 and TW at values that satisfy: CAPW≧TW×T1