One aspect of the invention relates to a method of manufacturing a flash memory device in which Vss lines are salicided prior to forming memory cell stacks. According to the invention, silicide is aligned to the Vss lines by a layer of temporary material, such as a silicon nitride layer, patterned to form dummy gates. A dielectric layer can be deposited and planarized with the dummy gates prior to their removal. The dielectric layer facilitates selective removal of the dummy gates and formation of memory cell stacks that are properly aligned with the Vss lines and drain regions. The dummy gate concept can be used with methods of forming low resistance Vss lines other than saliciding. One advantage of the invention is that the memory cell stacks are not exposed to high temperature processing used in forming low resistance Vss lines.