发明授权
US06462580B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
失效
门电路和半导体电路来处理使用它们制造的低振幅信号,存储器,处理器和信息处理系统
- 专利标题: Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
- 专利标题(中): 门电路和半导体电路来处理使用它们制造的低振幅信号,存储器,处理器和信息处理系统
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申请号: US09749474申请日: 2000-12-28
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公开(公告)号: US06462580B2公开(公告)日: 2002-10-08
- 发明人: Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
- 申请人: Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
- 优先权: JP6-81324 19940420; JP7-52241 19950313
- 主分类号: H03K19096
- IPC分类号: H03K19096
摘要:
The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.