发明授权
- 专利标题: Clock generating apparatus and method thereof
- 专利标题(中): 时钟发生装置及其方法
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申请号: US09631293申请日: 2000-08-02
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公开(公告)号: US06463013B1公开(公告)日: 2002-10-08
- 发明人: Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
- 申请人: Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
- 优先权: TW88114438A 19990824
- 主分类号: G04F500
- IPC分类号: G04F500
摘要:
A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.
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