Method of reducing electrical shorts from the bit line to the cell plate

发明授权

US06468859B1 Method of reducing electrical shorts from the bit line to the cell plate 失效

标题翻译：减少从位线到电池板的电气短路的方法

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专利标题： Method of reducing electrical shorts from the bit line to the cell plate
专利标题（中）： 减少从位线到电池板的电气短路的方法
申请号： US09399592

申请日： 1999-09-20
公开(公告)号： US06468859B1

公开(公告)日： 2002-10-22
发明人: Kunal R. Parekh , Charles H. Dennison , Jeffrey W. Honeycutt
申请人： Kunal R. Parekh , Charles H. Dennison , Jeffrey W. Honeycutt
主分类号： H01L218242
IPC分类号： H01L218242

Method of reducing electrical shorts from the bit line to the cell plate

摘要：

A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

摘要（中）：

在电容器电池板被蚀刻和清洁之后，沉积出四乙基正硅酸盐（TEOS）形式的应力缓冲器和掺杂剂阻挡层，从而消除从位线到电池板的电短路。

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