发明授权
US06469536B1 Method and device for providing symetrical monitoring of ESD testing an integrated circuit
有权
用于提供集成电路的ESD测试的对联监测的方法和装置
- 专利标题： Method and device for providing symetrical monitoring of ESD testing an integrated circuit
- 专利标题（中）： 用于提供集成电路的ESD测试的对联监测的方法和装置
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申请号： US09690666申请日： 2000-10-17
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公开(公告)号： US06469536B1公开(公告)日： 2002-10-22
- 发明人: Thomas Kessler , Andreas Tausch , Fabian Kederer
- 申请人： Thomas Kessler , Andreas Tausch , Fabian Kederer
- 主分类号： G01R3126
- IPC分类号： G01R3126
摘要：
A method and a device (4) for testing an integrated circuit (DUT) uses a stress signal and surface monitoring. A stress signal generator (5) is connected to the integrated circuit (DUT) to apply the stress signal (v(t)) to the integrated circuit. A failure is observed in real time by monitoring the surface (6) of the integrated circuit (DUT) during a monitoring time window (&Dgr;T) by an emission microscope (10) having a controllable shutter (15). The time window has a predetermined relation with respect to the duration of the stress signal.