The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high memory access rates, the ASIC contains a TASK scheduler, which is implemented as hardware and which chronologically coordinates, in an appropriate manner, the processing of different TASKs on an ASIC internal processing means (EXU). Compared to conventional software control units for multitasking systems, this TASK scheduler which is implemented as hardware offers the advantage, among others, that the operating system is relieved of load, and an expensive memory architecture is not required.