发明授权
US06479851B1 Memory device with divided bit-line architecture 有权
具有分立位线架构的存储器件

  • 专利标题: Memory device with divided bit-line architecture
  • 专利标题(中): 具有分立位线架构的存储器件
  • 申请号: US09573070
    申请日: 2000-05-16
  • 公开(公告)号: US06479851B1
    公开(公告)日: 2002-11-12
  • 发明人: Jae Jin Lee
  • 申请人: Jae Jin Lee
  • 主分类号: H01L27108
  • IPC分类号: H01L27108
Memory device with divided bit-line architecture
摘要:
The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.
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