Invention Grant
US06480913B1 Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter 有权
具有MUX选择输入的数据定序器,用于使用两个异或逻辑门和计数器转换输入数据流和特定的输出数据流

  • Patent Title: Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter
  • Patent Title (中): 具有MUX选择输入的数据定序器,用于使用两个异或逻辑门和计数器转换输入数据流和特定的输出数据流
  • Application No.: US09353894
    Application Date: 1999-07-15
  • Publication No.: US06480913B1
    Publication Date: 2002-11-12
  • Inventor: Anand C. Monteiro
  • Applicant: Anand C. Monteiro
  • Main IPC: G06F700
  • IPC: G06F700
Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter
Abstract:
A system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. The system includes, among other things, a data sequencer for sequencing the input data stream and a counter. The sequencer includes a select input having a first number of selection input locations, a data input for receiving the digital data stream, and output for transmitting the output data stream. The counter includes the first number of selection outputs. A first logic element and a second logic element are coupled to a number of the selection inputs of the sequencer and a number of the selection outputs of the counter. The first and second logic elements control the data sequencer such that the input data stream in converted into the second format.
Information query
Patent Agency Ranking
0/0