A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment.