发明授权
US06482685B1 Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step 失效
并入多层通道钝化工艺的低温多晶硅薄膜晶体管的制造方法

  • 专利标题: Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step
  • 专利标题(中): 并入多层通道钝化工艺的低温多晶硅薄膜晶体管的制造方法
  • 申请号: US10037014
    申请日: 2001-12-31
  • 公开(公告)号: US06482685B1
    公开(公告)日: 2002-11-19
  • 发明人: Chih-Chiang ChenKun-Chih Lin
  • 申请人: Chih-Chiang ChenKun-Chih Lin
  • 主分类号: H01L29786
  • IPC分类号: H01L29786
Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step
摘要:
A method for fabricating a low temperature polysilicon thin film transistor incorporating a multi-layer channel passivation stack, and for activating dopant ions in a polysilicon gate in the TFT structure has been described. In the method, a multi-layer channel passivation stack consisting of a first insulating material layer, a metal layer and a second insulating material layer are first deposited on a polysilicon gate to shield a channel region in the gate during a laser irradiation process for activating the dopant ions in the gate. Any damages to the channel region of the polysilicon gate by the laser irradiation or the rapid thermal annealing step can be avoided, as well as the dopant impurity out-diffusion and lateral diffusion problems.
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