发明授权
- 专利标题: Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction
- 专利标题(中): 在完成前一同步指令之前推测加工指令的方法和系统
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申请号: US09161640申请日: 1998-09-28
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公开(公告)号: US06484230B1公开(公告)日: 2002-11-19
- 发明人: Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
- 申请人: Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
- 主分类号: G06F1300
- IPC分类号: G06F1300
摘要:
A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed. The flush occurs because the data returned to the local processor due to a “cacheable hit” subsequent to the synchronization instruction was out of order with the snoop and the processor must flush the data and go back out to the system bus for the new data.
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