A controller interrupts and restarts writing data from a buffer memory to a medium and prevents buffer underrun errors. The controller includes an address memory for storing a recording medium address or a buffer memory address, which indicate the location of the data when the interruption occurred. A synchronizing circuit sequentially reads data from the recording medium and data from the buffer memory prior to the interruption while synchronizing the written data and the stored data. A restart circuit restarts writing data when the recording medium address or the buffer memory address matches the address stored in the address memory.