发明授权
- 专利标题： Logic verification method and apparatus for logic verification
- 专利标题（中）： 用于逻辑验证的逻辑验证方法和装置
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申请号： US09630412申请日： 2000-08-01
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公开(公告)号： US06490710B1公开(公告)日： 2002-12-03
- 发明人: Yasushi Wada
- 申请人： Yasushi Wada
- 优先权： JP2000-104836 20000406
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
After a logic verification is made in a low-hierarchical block, a logic verification is made in a high-hierarchical block circuit in a state that the low-hierarchical block is not the subject of comparison. Even if the number of input ports in the low-hierarchical block increases due to a change of the circuit, logical equivalence of the high-hierarchical circuit is verified by using equivalence information of the input ports.
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