发明授权
US06492679B1 Method for manufacturing a high voltage MOSFET device with reduced on-resistance
有权
制造具有降低的导通电阻的高压MOSFET器件的方法
- 专利标题: Method for manufacturing a high voltage MOSFET device with reduced on-resistance
- 专利标题(中): 制造具有降低的导通电阻的高压MOSFET器件的方法
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申请号: US09920655申请日: 2001-08-03
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公开(公告)号: US06492679B1公开(公告)日: 2002-12-10
- 发明人: Mohamed Imam , Joe Fulton , Zia Hossain , Masami Tanaka , Taku Yamamoto , Yoshio Enosawa , Katsuya Yamazaki , Evgueniy N. Stefanov
- 申请人: Mohamed Imam , Joe Fulton , Zia Hossain , Masami Tanaka , Taku Yamamoto , Yoshio Enosawa , Katsuya Yamazaki , Evgueniy N. Stefanov
- 主分类号: H01L2976
- IPC分类号: H01L2976
摘要:
A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate region (105). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the “on” state. The MOSFET device further has a p-top layer (108) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.
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