A plasma display panel including a partition wall (35) arranged between a front substrate (10) and a back substrate (13), and having vertical walls (35a) extending in the column direction and transverse walls (35b) extending in the row direction to define a discharge space (S) into each discharge cell (C) in the row direction and the column direction. A clearance (SL) extending in parallel to the row direction divides the transverse wall (35b) situated between the adjacent discharge cells (c) respectively in the column direction to each other. A groove (11Aa) formed in the additional dielectric layer (11A) makes communication between the inside of the clearance (SL) and the inside of the adjacent discharge cells (C) in the column direction.