发明授权
US06492833B1 Configurable memory design for masked programmable logic 有权
可配置的可编程逻辑存储器设计

Configurable memory design for masked programmable logic
摘要:
A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM. With the preload feature, the invention can emulate a ROM, a preloaded RAM, or looktip table logic functions as well as conventional RAM. Further, BIST allows for testing of the RAM without the needs for external support.
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