发明授权
US06496550B1 Time interleaved digital signal processing in a read channel with reduced noise configuration
有权
在具有降低的噪声配置的读通道中的时间交错数字信号处理
- 专利标题: Time interleaved digital signal processing in a read channel with reduced noise configuration
- 专利标题(中): 在具有降低的噪声配置的读通道中的时间交错数字信号处理
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申请号: US09444340申请日: 1999-11-19
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公开(公告)号: US06496550B1公开(公告)日: 2002-12-17
- 发明人: Melchiorre Bruccoleri , Marco Demicheli , Daniele Ottini , Alessandro Savo
- 申请人: Melchiorre Bruccoleri , Marco Demicheli , Daniele Ottini , Alessandro Savo
- 优先权: EP98830718 19981201
- 主分类号: H04L2708
- IPC分类号: H04L2708
摘要:
A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof. The conversion channel further includes an offset circuit for compensating an offset in the pair of analog-to-digital converters in the time interleaved analog-to-digital converter. The offset circuit is controlled by the digital post-processing circuit, and includes first and second distinct offset compensating circuits independently controlled by the digital post-processing circuit.