The present invention may be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing and provides an optimum arrangement along the flow of information in the case where a frame buffer, a command memory and an image processor are incorporated in one chip in order to improve the drawing performance of an image processing device. Thereby, unnecessary drawing-around of wiring is eliminated and it is possible to reduce the chip area. Further, since the wiring length is shortened, signal delay becomes small, thereby enabling a high-speed operation.